The present invention relates to extraction of audio data from a serial digital video signal, and more particularly to a phase locked loop chain for locking audio sampling to serial digital component video timing that reduces clock jitter to provide high resolution digitization of the audio data.
A serial digital video signal that conforms to the SMPTE 259M standard, for example, may include up to four channels of audio data. The clock for the serial digital video signal is inherent in the serial digital video signal, and is recovered from the serial digital video signal using a wide bandwidth phase locked loop. Any clock jitter is passed by the wide bandwidth phase locked loop. The recovered clock is then input to an audio sample clock generator to generate an audio sample clock using a second wide bandwidth phase locked loop. Any jitter input to the audio sample clock generator from the recovered clock appears in the audio sample clock.
Digitization of audio to sixteen (16) bits of resolution, for example, requires an audio sample clock with peak to peak jitter in the 100 picosecond (ps) range. However often the recovered clock has a jitter content much greater than 100 ps. This results in distortion of the audio signal generated by the audio data.
What is desired is a phase locked loop chain for locking audio sampling to serial digital component video timing that reduces clock jitter to provide high resolution recovery of the audio data from a serial digital video signal.